TI targets sensors with system-on-chip

Radar image

A system-on-chip launched this week by Texas Instruments targets military and avionics applications, among other markets, promising to reduce the size and power consumption of digital equipment while boosting performance in areas like high-speed data acquisition.

TI's Keystone SoC integrates a standard interface that helped reduce the overall device footprint. The chipmaker's digital signal processor was combined with an ARM multicore Cortex processor. Each chip delivers 1.2 GHz of processing power.

The SoC design also is a challenge to field-programmable gate array technology, which the company says is more power hungry. TI claims its approach represents an alternative to FPGAs by using less power while delivering roughly equivalent programmability.

TI said it is seeing initial interest from the avionics and military radar sectors.

For sensors, the Keystone SoC programmability allows it to handle a variety of analog-to-digital, digital-to-analog conversions along with analog front ends used to acquire and convert signals and generate data at high speeds. For radar applications, TI said a separate coprocessor module is accessible across its DSP cores to accelerate computations. These DSP computations are required for military systems such as radars.

FPGAs have been widely used as hardware accelerators in military sensor applications. Among the advantages of the technology is reduced system latency that can help decrease sensor vulnerability to threats like jamming. They also help increase sensor resolution in increasingly cluttered urban environments.

FPGA and SoC proponents differ on which technology is best suited to reducing size, weight and power consumption.

Dallas-based TI claims its SoC approach cuts power consumption in half while reducing the system footprint by two thirds. The chipmaker also claims software programmability speeds up system design times.

The standard serial interface used in the new SoC, designated JESD204B (PDF), connects high-speed data converters and the digital processor. TI said integration of a sensor's digital front end (DFE) with the standard interface permits changing filters through software programmability as a way to tweak sensors and other systems.

The programmable SoC allows designers to modify DFE configurations after deployments, and multiple configurations can be stored in DDR or flash memory. That means configuration changes can be made on days rather than weeks using FPGAs, TI claimed.

The chipmaker said the programmable SoC is currently being sampled and would be generally available in the third quarter of this year.

About the Author

George Leopold is a contributing editor for Defense Systems and author of Calculated Risk: The Supersonic Life and Times of Gus Grissom."Connect with him on Twitter at @gleopold1.

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